Ask an Expert Webinar: Debugging with Signal Tap for Intel® FPGAs

Debugging with Signal Tap for Intel® FPGAs

Join us to get your questions answered by an Intel expert!
This is your chance to come ask an expert about the new features in the Signal Tap Logic Analyzer in the Intel® Quartus® Prime Software, including more intuitive node-tapping with Signal Preservation, faster interations using Incremental Signal Tap, increasing visibility into your design with Simulator-Aware Signal Tap, and more. This is an interactive session where you can come and get answers to questions, or interact with other like-minded designers who are using Signal Tap to analyze and debug their designs.

Note: The session will be in English. It is part webinar part question-and-answer format, and will be recorded. Participation is voluntary, and participants will be informed before recording begins. The recording will be posted to the Intel website for use as training material for the public.

About the Signal Tap Logic Analyzer
The Signal Tap Logic Analyzer is used to probe and debug the behavior of internal signals during normal device operation, without requiring extra I/O pins or external lab equipment. The Signal Tap logic analyzer captures data continuously from the signals you specify while the logic analyzer is running. You specify trigger conditions that start or stop data capture which, when met, transfer data and display it for analysis and debug. The Signal Tap Logic Analyzer is a powerful and flexible tool that novices and experts can use to get their designs to production faster.

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Meet Your Expert

Steve Strell

Steven Strell is an expert on using the Signal Tap Embedded Logic Analyzer. He has been at Intel for 16 years and in the FPGA Training group for 14 of those years. In that time, he has created or been a part of many of the free online trainings and instructor-led classes available. Chances are if you’ve registered for an online training, you’ve heard his voice! Steve has taught numerous classes in-person and online to hundreds of FPGA designers covering a wide variety of topics. His specialty areas include the hardware design tools found in the Intel® Quartus® Prime software, such as Platform Designer, and debugging tools like the Signal Tap embedded logic analyzer. He has also created training material on power analysis and optimization, block-based design flows, such as partial reconfiguration, and external memory interfaces. He is also a frequent contributor to the Intel community forums.