Ask an Expert Webinar: Arm* Development Studio for Intel® SoC FPGA

Tuesday, September 28, 2021
9am-10am PDT / 16:00-17:00 GMT

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Arm Development Studio for Intel® SoC FPGAs

Join us to get your questions answered by an Intel expert!
This is your chance to come ask an expert about the Arm Development Studio for Intel® SoC FPGAs, an embedded C/C++ development toolchain designed specifically for Arm-based SoCs such as those found in Intel® SoC FPGAs. This is an interactive session where you can come and get answers to questions, or interact with other like-minded designers who are working on embedded development with Arm SoCs.

Note: The session will be in English. It is part webinar part question-and-answer format, and will be recorded. Participation is voluntary, and participants will be informed before recording begins. The recording will be posted to the Intel website for use as training material for the public.
About Arm Development Studio for Intel® SoC FPGAs
In this session, we will present an overview of Arm Development Studio for Intel® SoC FPGAs (Arm DS), a comprehensive suite of software development and debug tools including an IDE, compiler, debugger, tracer, profiler, and more. Time for questions and answers will be provided. We will discuss using Arm DS to compile, debug and analyze embedded C code for Arm processors. A live demonstration will showcase various aspects of the tool operation: how to set up a debug connection to a device, how to set up a breakpoint, how to view disassembled code, and how to run a .ds script.

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Meet Your Expert

Chris Martin

Chris Martin has over 25 years of embedded and SoC industry experience. He has worked on software, design and verification teams for various companies creating Arm-based SoC/FPGA designs and embedded software. Currently, Chris is the senior manager of the North American specialist FAEs for Arm. He also serves as the specialist FAE for Arm software development and debug tools. He focuses on helping customers debug embedded software during the development cycle for their FPGA and SoC designs.

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