Choose from Two Sessions
Session 1: Wednesday, May 26, 2021
8:00am - 9:00am, Pacific Daylight Time
Session 2: Thursday, May 27, 2021
9:30am - 10:30am, India Standard Time
Register below.
Join us to get your questions answered by an Intel expert!
This is your chance to come ask an expert about the Platform Designer tool in the Intel® Quartus® Prime Software. This is an interactive session where you can come and get answers to questions, or interact with other like-minded designers who are using Platform Designer. It doesn’t matter what level you’re at! If you’re new to Platform Designer, come and find out more. If you’ve been using Platform Designer for a while, come ask some of those detailed questions you’ve been wanting answered. This is an opportunity to explore Platform Designer together.Note: The session will be conducted in English.
About Platform Designer
Platform Designer saves significant time and effort in the FPGA design process by automatically generating interconnect logic to connect intellectual property (IP) functions and subsystems. Platform Designer utilizes a powerful hierarchical framework to offer fast response times for interconnecting large systems, while also providing support for blackbox entities. This enables Platform Designer to provide fast response times while opening systems and creating new connections by regenerating or operating on IP blocks that have changed. The Platform Designer tool also supports a variety of design entry methods, such as register transfer level (RTL) languages, block-based design entry, schematic entry, and black boxes.
Required Fields(*)
Steven Strell is an expert on using Platform Designer. He has been at Intel for 15 years and in the FPGA Training group for 13 of those years. In that time, he has created or been a part of many of the free online trainings and instructor-led classes available. Chances are if you’ve registered for an online training, you’ve heard his voice! Steve has taught numerous classes in-person and online to hundreds of FPGA designers covering a wide variety of topics. His specialty areas include the hardware design tools found in the Intel® Quartus® Prime software, such as Platform Designer, and debugging tools like the Signal Tap embedded logic analyzer. He has also created training material on power analysis and optimization, block-based design flows, such as partial reconfiguration, and external memory interfaces. He is also a frequent contributor to the Intel community forums.