Intel

Get tips and tricks for closing timing faster in an Intel® FPGA design.

Join us to get your questions answered by an Intel expert!

This is your chance to come ask an expert about tricks and techniques for achieving timing closure with the Intel® Quartus® Prime Software. This is an interactive session where you can come and get answers to questions, or interact with other like-minded designers who are working on timing analysis and closure in their designs. It doesn’t matter what level you’re at! If you’re new to designing FPGAs and creating timing constraints, come and find out more. If you’ve been designing FPGAs for some time and have a number of shipping products under your belt, come ask some of those detailed questions you’ve been wanting answered or share your knowledge. This is an opportunity to explore some of the tips, tricks, techniques, and best practices that will help you get to timing closure faster.

Note: The session will be in English. It is in a question-and-answer format, and will be recorded. Participation is voluntary, and participants will be informed before recording begins. The recording will be posted to the Intel website for use as training material for the public.

About Timing Closure

One of the greatest and most frustrating FPGA design challenges is closing timing. It is very common to find, after performing a complete timing analysis on an FPGA design, that one or more timing reports indicate a timing failure. How can this be corrected? There are many techniques, including thoroughly analyzing the design for common timing failures, adjusting settings and assignments according to tool recommendations, selecting the correct clock resources, and adjusting HDL code for optimal performance. There are many different tools and reports within the Intel® Quartus® Prime Pro Development Software that will help you get the best performance out of your design and get to timing closure faster.

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Meet Your Expert

Steven Elzinga

Steven Elzinga has been in the Intel FPGA Training group for nearly 4 years. Prior to that, he designed video processing cores in FPGAs and got his start in FPGAs as an applications engineer. His current primary focus is timing closure but teaches on a variety of classes including HLS, timing analysis, and introductory courses. He is also a frequent contributor to the Intel community forums.